Thanks to the VEGAS project, the NG-MEDIUM device has gone from a recently fabricated device to a fully space-qualified solution for space applications. The device also has gone from unknown to popular in both academic and industry circles, being a huge success in the space market.
The NG-MEDIUM has been chosen for a number of space projects, including at least one satellite constellation.
A specific workshop, the BRAVE FPGA days, has been born during the VEGAS project, with great success in terms of attendees, sparking the interest of many actors in the space sector.
Also the software tools have been greatly improved with the input from the rest of the partners.
At the end of the VEGAS project, Europe has now a fully-european FPGA, available without any import restrictions, that can be used for space missions and other harsh environments.
NanoXplore has coordinated the project and supported the partners in the consortium.
ST Microelectronics has been in charge of the qualification of the NG-MEDIUM device.
The successful qualification ensures the device is adequate and suitable to be used in space missions without any additional analysis, and with cost and lead time efficiency.
This is essential to penetrate the space market, and puts the NG-MEDIUM on par with other non-european FPGA devices in terms of readiness for new space missions, but with the extra availability provided by the non-dependency on entities outside europe and the lack of any import restrictions.
Thales Alenia Space - España (Spain) has been in charge of coordinating the Radiation Evaluation & Mitigation work package of the project.
TAS-E has also developed the Test Vehicle PCB board that has been used in the radiation experiments.
TAS-F has mainly worked on the evaluation of NanoXmap V2 by comparing the performances of NG-MEDIUM FPGA with other targets.
Resource utilization results are encouraging compared to other technologies. Indeed, the NanoXmap synthesis process seems to be as efficient or more efficient than competing tools. The number of DFF and the number of LUT are closed to the expected ones. However, improvements on the routing process have to be made. At the end of the flow, too much functional elements are used. A lot of LUT are used in order to route other instances (DFF, CY, RF, etc.). Then, most of the time, the placing process fails when the percentage of functional element reaches 75% - regarding the tested designs during this evaluation timeframe. Finally, a RTAX2000 design mostly fits into a NG-MEDIUM device.
Process time is a bit longer than some other tool set. Hence, this is a slight difference for design over 50% occupancy of the NG-MEDIUM.
Concerning static timing analysis, overall reached frequency is not really high. However, results on these designs may be improved with future NanoXmap versions. Indeed, the static timing analyzer is not optimized and the timing constraints do not really seem to be taken into account.
Thales Alenia Space - France has also worked on the validation of hardware features in the FPGA.
The aim of the activity on the ‘VEGAS Systematic FPGA function validation’ WP1 can be divided in 2 main parts.
First of all the tool suite NXmap has been tested on 2 digital signal processing algorithms. The tool version used are going from 2.8.1 to 2.9.1. The design have been synthesized, place, routed and analyzed in timing. Results in terms of resource usage were in line with the design sizes. Concerning frequency performances the tool’s given frequencies were not impacted by frequency constraints (called ‘timing driven’ algorithm). Run time of the tool suite was around 30 minutes for a design that represent 65% of the NG-MEDIUM capacity. The evolution of the tool has been significant over the versions.
In a second time, the validation of the NG-MEDIUM macroblocks cells is performed on the evaluation kit board. The tested macroblock cells are the NX_FE, NX_DSP, NX_CY, NX_WFG, NX_PLL. The method applied was to perform tests on the board using all possible configuration of a single macroblock and random test vectors. The results were compared to the simulation model of the macroblocks and to a software model design using the macroblocks’ datasheet description. At the end of the tests; all results were in line with the simulation and their description in the datasheet. No errors were found in the FPGA matrix.
In the frame of VEGAS an inverse FFT Radix-2 and Radix 4 and a Digital Down Converter (DDC) were tested. The VHDL code for the Radix-4, Radix-2 and Digital Down Converter were provided from another project done at Airbus. The algorithms were first developed in Matlab as Simulink block schemes and then they were automatically translated to VHDL thanks to HDL coder and HDL workflow advisor.
Table 1: Maximum clock speed after simulations with linear timing optimisations, comparison between NanoXPython 1.4.0 and 1.5.0.
Table 2: Maximum clock speed after simulations with reversed timing optimisations, comparison between NanoXPython 1.4.0 and 1.5.0.
Table 3: Maximum clock speed after simulations with different architectures, linear timing, IFFT Radix-2 linear
Table 4: Maximum clock speed after simulations with different architectures, reverse timing, IFFT Radix-2 reverse
An Airbus-proprietary existing design of a GNSS receiver, based on an AGGA-4 processor, was tested. Since the original design was far too large for the BRAVE, it was split into two parts and only the most important blocks were taken and tested.
Table 5: AGGA-4 Part 1 timing results with NanoXPython 1.4.0 and 1.5.0.
Table 6: AGGA-4 Part 2 timing results (ExtClk, one channel) with NanoXPython 1.4.0 and 1.5.0.
Table 7: Comparison of results obtained with GNSS 1 channel between BRAVE and RTG4, GNSS with 1 channel
Table 8: Comparison of results obtained with GNSS 2 channel between BRAVE and RTG4, GNSS with 2 channels
Universidad de Sevilla has developed a fault injection platform for the BRAVE FPGA, called the FTU-VEGAS. This platform is of interest for researchers and designers, in order to study design robustness in FPGAs, find optimal selective hardening schemas, and explore the possibility of using the NG-MEDIUM FPGAs in harsher-than space scenarios. By using a PCIexpress extension cable, the platform can also be used in radiation experiments, in which it operates just controlling the target FPGA and the input/output test vectors, leaving the error insertion to the radiation beam.
The European Space Agency has already shown interest in this platform.
USE has also developed the triple-logic VHDL package, an open-source package to implement fine-grain selective mitigations on a design, just by changing the datatype of the object (signal, port or variable). This package is the perfect complement for a fault injection platform, since the fault injection campaigns will identify the most sensitive elements in the design, which can then be easily hardened using the package.
Politecnico di Torino has developed an adaptation of its static analysis & routing Veriplace tool to the NG-MEDIUM FPGA.
This tool allows to separate redundancy domains to assure that a single error in the FPGA configuration plane will not propagate simultaneously to more than one redundancy domain, for example, in the case of a short-circuit in a switching matrix.
VEGAS project has received funding from the European Union's Horizon 2020 research and innovation programme under grant agreement N° 687220